(1) Field of the Invention
The present invention relates to a method used to fabricate a storage node electrode, for a crown shaped, DRAM capacitor structure.
(2) Description of the Prior Art
The major objectives of the semiconductor industry are to continually improve the performance of semiconductor devices, while still maintaining, or decreasing the cost of fabricating these same semiconductor devices. These objectives have been successfully addressed by the ability of the semiconductor industry to produce semiconductor chips with sub-micron features, or micro-miniaturization. Smaller features allow a reduction in performance degrading capacitances and resistances to be realized. In addition smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of a source/drain of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of a billion cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures.
Two methods that have been used to increase STC capacitance, while still decreasing the lateral dimension of the capacitor, have been the use of rough, or hemispherical grain (HSG), silicon layers, and the use of crown shaped STC structures. First, referring to the crown shaped STC structures, the creation of a polysilicon, or amorphous silicon, storage node electrode structure, comprised of both vertical and horizontal silicon features, results in a greater electrode surface area then would have been achieved with counterparts fabricated without vertical features. Secondly the use of an HSG silicon layer, comprised of convex and concave features, and used for the top layer of the storage node electrode structure, again results in a greater degree of surface area then counterparts fabricated with smooth silicon layers. Therefore the combination of a crown shaped STC structure, comprised with a top layer of HSG silicon, residing on the crown shaped storage node structure, is an attractive option for high density DRAM devices.
This invention will describe a novel process for the fabrication of a crown shaped STC structure, featuring an HSG silicon layer, thus offering the attractive combination in regards to increased capacitor surface area. This invention will describe the use of a crown shaped storage node structure, covered by a HSG silicon layer, where crown shaped storage node structure is formed from a composite amorphous silicon layer, comprised of three amorphous silicon layer, all deposited in situ, in a low pressure chemical vapor deposition, (LPCVD), tool, with a heavily doped layer located between two lightly doped amorphous silicon layers. The use of the lightly doped amorphous silicon surfaces allow selective HSG seeding and growth formation, on the exposed, lightly doped surfaces of the crown shaped, storage node structure. In addition the use of the heavily doped amorphous silicon layer supplies the dopants needed to minimize a capacitance depletion phenomena. This invention will also describe a vapor pre-clean procedure, preparing the exposed lightly doped amorphous silicon surfaces, for the in situ deposition of HSG seeds. Prior art such as Thakur et al, in U.S. Pat. No. 5,656,531, or Zahurak et al, in U.S. Pat. No. 5,639,685, describe a processes for fabricating HSG layers, however these prior art do not describe the process offered in this present invention, that is the use of a three layer, amorphous silicon, crown shaped, storage node structure. In addition these references do not describe a hydrofluoric vapor pre-clean procedure, followed by an in situ deposition of HSG seeds, for selective HSG growth in a conventional LPCVD system.